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VHDL Environment for Floating point Arithmetic Logic Unit - ALU Design and Simulation

Author Affiliations

  • 1 Department of Electronics and communication, Shri Satya Sai Institute of technology and Science, Sehore, MP, INDIA

Res. J. Engineering Sci., Volume 1, Issue (2), Pages 1-6, August,26 (2012)

Abstract

VHDL environment for floating point arithmetic and logic unit design using pipelining is introduced; the novelty in the ALU design. Pipeling provides a high performance ALU. Pipelining is used to execute multiple instructions simultaneously. In top-down design approach, four arithmetic modules, addition, subtraction, multiplication and division are combined to form a floating point ALU unit. Each module is divided into sub- modules. Two selection bits are combined to select a in the ALU design are realized using VHDL, design functionalities are validated through VHDL simulation. Synthesis and simulation result find out in the Xilinx12.1i platform.

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