VHDL Environment for Floating point Arithmetic Logic Unit - ALU Design and Simulation

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VHDL Environment for Floating point Arithmetic Logic Unit - ALU Design and Simulation

Author Affiliations

¹ Department of Electronics and communication, Shri Satya Sai Institute of technology and Science, Sehore, MP, INDIA

Res. J. Engineering Sci., Volume 1, Issue (2), Pages 1-6, August,26 (2012)

Abstract

VHDL environment for floating point arithmetic and logic unit design using pipelining is introduced; the novelty in the ALU design. Pipeling provides a high performance ALU. Pipelining is used to execute multiple instructions simultaneously. In top-down design approach, four arithmetic modules, addition, subtraction, multiplication and division are combined to form a floating point ALU unit. Each module is divided into sub- modules. Two selection bits are combined to select a in the ALU design are realized using VHDL, design functionalities are validated through VHDL simulation. Synthesis and simulation result find out in the Xilinx12.1i platform.

References

ANSIWEE std 754-1985, IEEE standard for binary Floating-point arithmetic, IEEE New York (1985)
Daumas M. and Finot C., Division of Floating point Expansions with an application to the computation a Determinant, journal Universal computer Science, 5, (2000)
AMD athlon processor technical brief, Advance Micro DevicesInc, Publication no.22054, Rev.D,Dec (1999)
Chen S., Mulgeew B. and Grant P.M., A Clustering technique for digital communications Channel equalization using radial basis function Networks, IEEETran. Neural Networks, , 570-578 (1993)
Pipeline Floating Point ALU Design using VHDL Mamu Bin Ibne Reaz, MEEE, Md. Shabiul Islam, MEEE, Mohd. S.Sulaiman, MEEE, Multimedia University, ICSE2002 Proc. (2002)
Floating Point-www.wikipedia.com (2012)
Proc Design Trade-Offs in Floating-Point Unit, Implementation for Embedded and Processing-In-Memory System, Taek-Jun Kwon, Jeff Sondeen, Jeff Draper SC Information Sciences Institute,4676 Admiralty Way Marina del Rey, CA 90292 U.S.A. (2005)
Floating Point ALU with parallel paths,Kennth Y.Ng, Saratoga kallif,518452,may (1990)
VHDL Tutorial,Peter J. Ashenden EDA Consultant, Ashenden Designs Pty. Ltd.,www.ashenden.com. © 2004 by Elsevier Science (USA)
Arithmetic and logic design, Wikipedia (2012)

[ref1] ANSIWEE std 754-1985, IEEE standard for binary Floating-point arithmetic, IEEE New York (1985)

[ref2] Daumas M. and Finot C., Division of Floating point Expansions with an application to the computation a Determinant, journal Universal computer Science, 5, (2000)

[ref3] AMD athlon processor technical brief, Advance Micro DevicesInc, Publication no.22054, Rev.D,Dec (1999)

[ref4] Chen S., Mulgeew B. and Grant P.M., A Clustering technique for digital communications Channel equalization using radial basis function Networks, IEEETran. Neural Networks, , 570-578 (1993)

[ref5] Pipeline Floating Point ALU Design using VHDL Mamu Bin Ibne Reaz, MEEE, Md. Shabiul Islam, MEEE, Mohd. S.Sulaiman, MEEE, Multimedia University, ICSE2002 Proc. (2002)

[ref6] Floating Point-www.wikipedia.com (2012)

[ref7] Proc Design Trade-Offs in Floating-Point Unit, Implementation for Embedded and Processing-In-Memory System, Taek-Jun Kwon, Jeff Sondeen, Jeff Draper SC Information Sciences Institute,4676 Admiralty Way Marina del Rey, CA 90292 U.S.A. (2005)

[ref8] Floating Point ALU with parallel paths,Kennth Y.Ng, Saratoga kallif,518452,may (1990)

[ref9] VHDL Tutorial,Peter J. Ashenden EDA Consultant, Ashenden Designs Pty. Ltd.,www.ashenden.com. © 2004 by Elsevier Science (USA)

[ref10] Arithmetic and logic design, Wikipedia (2012)